1. Field of the Invention
The present invention relates to a semiconductor device in which inner leads and a chip are electrically connected and, more particularly, to a semiconductor device, having improved inner leads, which is suitable for a large-capacity memory.
The present invention also relates to a lead frame suitable for a semiconductor device having a large-capacity memory.
2. Description of the Related Art
As in the case with recent micropatterning of semiconductor devices, chip size is also being reduced. Along with the reduction in chip size, the pitch of bonding pads on a chip, which are to be electrically connected to a lead frame by bonding wires, also becomes narrow.
As shown in FIG. 3A, in a conventional semiconductor device, to form a usable package as a final product from a chip having a device thereon, a chip 32 is bonded on a lead frame 31, and bonding pads 39 on the chip 32 are electrically connected to inner leads 37 of the lead frame 31 by bonding wires 33.
After all the bonding pads 39 are connected to the inner leads 37, the resultant structure is covered with a resin. The lead frame 31 is cut into a predetermined shape, and terminals to be connected to an external device are formed, thereby forming the package as the final product.
In FIG. 3A, if the lead frame 31 is completely flat, the bonding pad 39 on the chip 32 mounted on the lead frame 31 is at a higher position than the inner lead 37 by the thickness of the chip 32. The bonding pad 39 must be connected to the inner lead 37 by the bonding wire 33 over a step, resulting in a complex process. In addition, the bonding wire 33 may be cut off by the edge of the chip 32.
To solve these problems, in the conventional semiconductor device as shown in FIG. 3A, a die pad portion 35 is formed in the lead frame 31 to form a step corresponding to the thickness of the chip 32 between the die pad portion 35 and the inner lead 37. More specifically, the die pad portion 35 is formed to be integrated with the lead frame 31, and a step portion 38 is formed in a fixing inner lead 36 connected to the die pad portion 35. With this arrangement, the die pad portion 35 can be formed at a lower position than the inner lead 37. Since the upper surface of the chip 32 can be made almost flush with the inner lead 37, the above-described problem can be avoided.
However, in a micropatterned semiconductor device, a plurality of power supply pads may be formed among the bonding pads 39 on the chip 32, as shown in FIG. 3B. In some cases, power supply leads 37a of the inner leads 37 and the power supply pads cannot be formed in one-to-one correspondence under the required spatial limitations. In such a case, a plurality of, e.g., four bonding pads are connected to one power supply lead 37a (FIG. 3B).
In general, the shape and size of the lead frame do not change even when the chip size is reduced, because the pin arrangement or the like is based on a standard or defacto standard, and interchangeability between pins must be maintained. When the chip size is reduced, the chip is arranged at the center of the package, i.e., on a portion of the die pad portion 35 closer to the fixing inner lead 36, as shown in FIG. 3C. The interval of bonding pads denoted by "a" in FIG. 3B is designed on the basis of a minimum exposure size and often cannot be decreased anymore. In this case, the bonding pads are formed close together using a portion denoted by "b" in FIG. 3B where no bonding pads have been formed.
When all the bonding pads are formed at the interval "a" designed on the basis of the minimum exposure size to reduce the chip size, as shown in FIG. 3C, some bonding pads which have been on the lower side of the fixing inner lead 36, in the drawing, in a conventional semiconductor device having relatively large chip size may move to the upper side of the fixing inner lead 36.
In addition, when conditions for formation of a semiconductor device in the chip 32 are restricted and capacity is increased, a plurality of power supply pads or ground pads on the chip 32 cannot be formed close together in a region. For this reason, these pads may be formed at random intervals on the chip 32.
In this case, since the power supply leads and the power supply pads can hardly be formed in one-to-one correspondence, as described above, the power supply leads must be extended to cover the region where the power supply pads or ground pads are formed. However, when the power supply leads or ground leads are formed over a wide area, they may interfere with bonding wires to be connected to other inner leads, or the space for other inner leads cannot be ensured.